Semiconductor devices such as DRAM devices include a plurality of cells. Each of the DRAM cells has a cell capacitor and a cell transistor, which are electrically connected in series, and the cell transistor is electrically connected to a bit line. The cell transistor is turned on during a writing operation to transfer data corresponding to a bit line voltage to the cell capacitor. Further, the cell transistor is also turned on during a read operation to transfer data stored in the cell capacitor to the bit line. On the contrary, the cell transistor is turned off in a stand-by mode to retain data stored in the cell capacitor.
However, even though the cell transistor is turned off in a stand-by mode, the data stored in the cell capacitor (that is, an electrical charge) may be lost through various leakage current paths as time elapses. The leakage current paths are closely related to characteristics of the cell transistor. For example, if the so-called interface trap density that is generally known to exist between a gate insulating layer of the cell transistor and the surface of the semiconductor substrate increases or the channel length of the cell transistor decreases, the cell transistor may exhibit high leakage current when the cell transistor is turned off. Thus, the DRAM devices employ refresh circuits to periodically re-store desired data into the cell capacitors.
If the cell transistor shows high leakage current, a cycle time of the refresh operation may be reduced. In this case, power consumption of the DRAM device may increase. Thus, leakage current characteristic of the cell transistor should be improved in order to realize a low power DRAM device.
Most semiconductor devices including the DRAM devices are fabricated using a hydrogen alloy process as a back-end process. The hydrogen alloy process is very effective to reduce defects of a MOS transistor, particularly an interface trap density between a gate insulating layer and a surface of a semiconductor substrate. Thus, if the hydrogen alloy process is performed, the refresh characteristic of the DRAM device can be improved. In general, the hydrogen alloy process is performed after formation of metal interconnections and a passivation layer.
In order to improve an integration density and an operating speed of the DRAM device, a multi-layered metal technique has been widely used and the cell transistor has been gradually scaled down. In this case, a topmost metal layer used as a power line may be disposed over a cell array region of the DRAM device. The power line is typically designed to have a plate shape, thereby covering most of the cell array region. This is for minimizing voltage drop due to power line resistance. In this case, even though the hydrogen alloy process is performed, the planar type topmost metal layer covering the cell array region may prevent hydrogen atoms provided during the hydrogen alloy process from reaching the interface of the gate insulating layer of the cell transistor. Thus, when the multi-layered metal technique is employed in the DRAM device, there may be limited improvement in the refresh characteristic of the DRAM device.
A semiconductor device having a metal layer is described in U.S. Pat. No. 5,229,642 to Hara et al., entitled “Resin Molded Type Semiconductor Device Having a Conductor Film.” According to Hara et al., a metal guard ring is provided on an edge of a tetragonal semiconductor substrate, and the substrate having the metal guard ring is covered with a passivation layer. If the substrate having the passivation layer is encapsulated by a package process using a resin molding layer, the stress due to the resin molding layer may be concentrated on the passivation layer on four corner regions of the semiconductor substrate. As a result, cracks may be generated inside the passivation layer. Thus, Hara et al. provides a hole such as a slit in the metal guard ring on the four corner regions in order to alleviate the stress of the resin molding layer.